Invented by Zvi Or-Bach, Jin-Woo Han, Monolithic 3D Inc
The Monolithic 3D Inc invention works as followsA 3D Device, The device includes: a 1st level with logic circuits and a 2nd level with a plurality memory circuits. The first level is bonded into the 2nd level and the bonding includes oxide-to-oxide bonds.
Background for 3D semiconductor device, structure
This application relates generally to Integrated Circuit (IC), devices and fabrication techniques, but more specifically to multilayer (3D-Memory), devices and fabrication methodologies.
In the last 40 years there has been a significant increase in the functionality and performance of Integrated Circuits. This is largely due to the phenomenon known as “scaling?” This refers to the fact that component sizes, such as lateral or vertical dimensions, within ICs have been decreased (?scaled?) Each successive generation of technology. Complementary Metal Oxide Semiconductor ICs have two main types of components: wires and transistors. Typically, transistor performance and density improve with?scaling”. This has led to the above-mentioned improvements in IC functionality and performance. With?scaling?, however, the performance of interconnects (wires) that connect transistors decreases. Today, wires are dominating the performance, functionality, and power consumption of ICs.
The 3D stacking of chips or semiconductor devices is one way to address the wire problems. The transistors in ICs can now be placed closer together by arranging them in 3D instead of 2D (as it was in the 1990s). This allows for a reduction in wire length and a low delay.
There are many ways to build 3D-stacked integrated circuits and chips, including:
Toshiba, in a landmark paper at VLSI 2007, and IEDM 2007 presented techniques for constructing 3D memory which they called BiCS. Memory vendors have followed this work with variations and alternatives, mainly for non-volatile applications. For example, 3D-NAND is now referred to. These devices offer a significant manufacturing advantage by allowing the patterning multiple layers to be done in a single lithography step, which is usually “critical”. Most of these 3D Memory schemes rely on polysilicon as the active memory channel, which has higher performance variations from cell to cell and lower drive compared to a cell that uses a monocrystalline cell. At least in our U.S. Patent. Nos. These are included here by reference. We presented multiple 3D memories structures that were constructed using successive layer transfers and ion-cut techniques. We present multiple structures and methods for constructing 3D memory using monocrystalline channels by alternative methods. These methods include ion-cut and successive layer transfer. This structure combines the advantages of processing multiple layers in one lithography with the monocrystalline channel and lower construction costs.
In addition to the U.S. Patent No. Nos. Nos. 11,114,464, 10847,540 10,418,369 10,014,318, U.S. Patent application publication 2020013800, and U.S. Patent applications Ser. Nos. “Nos.
The invention could be directed at multilayer or three-dimensional integrated circuit (3D IC), devices and fabrication methods.
In one aspect, “a 3D device” is described as a device that includes: a first layer comprising logic and memory circuits; and a secondary level comprising memory and logic circuits. The first and second levels are bonded together, with oxide-to-oxide bonds.
In another aspect of a 3D Device, the device comprises: a first layer comprising logic cells; and a secondary level comprising a number of memory cell, wherein the first level is bonded with said second level. The bonded includes oxide to oxide bonding, and said logic circuits include at least one controller circuit and a variety of decoders circuits.
In another aspect of a 3D Device, the device comprises: a first layer comprising logic Circuits; and a 2nd level comprising a number of memory Circuits. Wherein said first and second levels are bonded together, said bonding being oxide to oxide, and said plurality memory circuits consisting of at least four independently-controlled memory arrays.
An embodiment of the invention or combinations thereof are now described using the drawings figures. Normal skill in the art will recognize that the descriptions and figures do not limit the invention. In general, the figures are not drawn at scale to facilitate clarity. These skilled people will also see that there are many other embodiments possible using the inventive principles described herein.
Some drawings may show process flows for building devices. A sequence of steps to build a device may include many structures, numerals, and labels. These may be shared between several steps. Some labels, numerals, and structures that were used in a particular step’s figure might have been described in previous steps’ figures.
Memory architectures consist of at least two types: NAND and NOR. NAND architecture offers higher density because the transistors that form the memory cells are connected in serial fashion with an external connection at both the beginning and the end of each cell string. This is illustrated in at most U.S. Pat. No. 8,114,757, FIGS. 37A-37G. NOR architectures can be less dense, but offer faster access. They could also work when the NAND architecture is not available. Individual NOR memory cells and its source and drain can both be accessed. No. 8,114,757, FIGS. 30A-30M.
The memory cell could be built with either conventional N or P type transistors, where channel doping could be of the opposite type to the source drain doping. Or the memory cell could use a junction-less transistor structure where the gate could completely deplete the channel in the off-state. The junction-less transistor may be attractive for certain architectures because it requires fewer processing steps or offers other advantages, such as a low leakage off state.
Some 3D Memory architectures use a horizontal memory transistor for example as shown in at least U.S. Patent. No. No. 8,114,757; at most FIGS. 37A-37G, and FIGS. 30A-30M. Other types of memory transistors may be used, such as the vertical memory transistors in the Toshiba BiCS architecture, as illustrated in at most U.S. Pat. No. 7,852,675.
Multiple methods for building 3D memory structures using horizontal transistors with junction-less transistors to form a NAND architecture and for general horizontal NAND or NOR architectures can be found in U.S. Pat. No. No. 8.114,757 in at most FIG. 33 and FIG. 37. This article will discuss multiple methods to create a multilayer silicon-oxide start structure that is equivalent to at least FIGS. 33D and 37D (of U.S. Patent. No. No. 8,114,757) without the use of an ion-cut Layer Transfer.
The starting structure could look similar to FIG. 41A of U.S. patent Ser. No. No. 1A. 1A. A base donor substrate 110 can be used to create a dual porous layer for future cutting layer 113. An epitaxial process could be used to produce a thick, crystalline layer 120. Future cut layer 113 could include two layers of porous silicon. An upper layer of porous silica may have microscopic pores with a diameter of just a few nanometers. Below this layer is formed a lower layer porous silicon whose pores may be several (or more!) times larger (similar to FIG. 23 of U.S. patent application Ser. No. No. 14/642,724), for the future?cut? “The epitaxial formation a relatively thick crystal layer 120 could involve successively altering dopants to support the next steps.
The thick crystalline layer 120 can then be transformed by anodizing to form a multilayer with alternating low porosity and high porosity, as shown in FIG. 1B, which is identical to FIG. 41B of Ser. No. 14/642,724. As described below, the alternating-porosity-multilayer can later be transformed into an alternating multilayer monocrystalline-Si over insulating SiO2. FIG. FIG. 1B shows a thick, crystalline layer 120 that has been through porous formation which creates multilayer structure 122. Multilayer structure 122 can include layers 144, layer 142, layer 140, layer 140 and layer 138. Layer 138 may also be included. Layer 136, layer 135, layer 134, and layer 132. Multilayer structure 122 could also include base donor wafer substrate 110 and porous cut layer 113, which can be used to transfer the multilayer structure fabricated over the target wafer. This may allow for the prefabrication of memory peripherals circuits on the target wafer. Multilayer structure 122 could also not include porous layer 113 if the transfer to a target Wafer is not planned. Layer 144 may be the remaining layer 120 after multi-layer processing. Alternating layers can have different porosity levels. Layers 132-136-140 could have porosity less than 30% or 40%, while layers 138, 138, and 142 could have porosity less than 50% or more than 60%. Or layers 132?136?140 could have porosity less than 55%, while layers 134?136?140 could be less than 55%. Layers 132?136, 140 could have porosity less than 55%, while layers 134?138, 142, 142 may contain porosity greater than 65% or another level depending on the process or engineering choice. Each layer could have a different porosity depending on its thickness or the number of sublayers.
The number of alternating layer in the multilayer structure could be as high as needed for a 3D memory, for example greater than 20, greater 40, greater 60, or even greater 100, or to transfer a subset multilayer structures on top of each other, to form the final structure. Porosity modulation can be achieved by, for instance, (1) changing the anodizing voltage, (2) changing the illumination while the silicon structure is in the anodizing phase, (3) first switching the doping during the epitaxial growth of layer 120, or (4) by etching and oxidizing multiple layers of SixGe1X/Si. The un-processed portion of layer 120 could be Layer 144. Here are a few embodiments for the method described above of forming a multilayer of c-Si/SiO2 from an alternated porous multilayer.
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