Samsung Electronics Co., Ltd. (Suwon-si, KR)

A pixel sensor detects the incident light and outputs the signal of sampling. A sampler compares the sampling signal with a ramp signal and outputs information on the length of the time-axis and a gray counter measures the length of the comparison signal, synchronizing it with a clock signal, and outputs digital numbers. The gray counter is comprised of a first flip-flop that divides the clock signal by 2 and produces a first gray code signal, a second flip-flop that delays the first data signal that is a four-divided signal of the clock signal and produces a second gray code signal. There is a third flip-flop, which delays the second gray code signal by two divisions and outputs a third gray code signal.

1. Field

Embodiments are related to the semiconductor device, and more specifically, to the gray-code generator as well as an image sensor comprising the same.

2. Description of Related Art

Counters transform a physical measurement that is effective, such as the brightness of light, strength of sound, and a time, into a digital signal.

The inventions are targeted at the image sensor. They include an pixel sensor that detects incident light and outputs an analog sample signal. A sampler designed for comparing the sampling signal with an output signal that is a ramp and produces the comparison signal with time-axis length information. Gray counter configured to measure the length of the signal while synchronizing it with the clock signal. A second flip-flop configured delay a first clock signal to four times and output another gray signal.

Embodiments can also be directed to a gray counter that produces a gray code count value in synchronization with an alarm signal, such as the first flip-flop that is configured to divide the clock signal by two and create a first gray signalcorresponding to the least significant bit of gray count as well as a Johnson counter configured to divide the clock signal by 4 and output an initial data signal; another flip-flop that is configured to delay the first data signal for the length of one duration of the clock signal, and to output an additional gray code signal as well as a third flip-flop designed to divide the second gray code signal in two and output a third gray code signal. Also, a plurality of flip-flops designed to generate an amount of count above the signal of the third gray based on the clock signal as well as the signal from the third gray code.

Embodiments can also be a gray counter that generates gray code count numbers in the synchronization of a clock signal. These include the following: A replica circuit designed to generate the first gray signal that is a minimum bitgray signal from a first clock signal. Another flip-flop that is configured for delaying a second clocksignal by as long as is possible, and then output two gray codes signals. A third flip-flop that is configured with the ability to divide the third gray code signal by 2 and produce a fourth code signal.

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