Cannabis Patents and Trademarks – Sandra Marie Johnson, David R. Welland, Cirrus Logic Inc

Abstract for “Pipelined analogue-to-digital (ADC), systems, methods and computer program products

“A pipelined digital-to-analog converter (ADC), is calibrated to produce an n-bit digital output that represents an n-2-bit binary word. Where?n? A large, selected positive integer, such as a number greater than ten (10). An analog-to-digital convertor (ADC), which has a number of stages, includes a stage input and output connection as well as a capacitor circuit that includes first and second predetermined capacitors C1 and C2 and a variable capacitance calibrator (Ccal). At a capacitor common point, the first and second capacitors are connected to one another. A capacitor common node is also connected with an amplifier input connection. An amplifier input connection is connected to a comparator input connection. A track and hold circuit is connected to an amplifier output connection. A source follower circuit is connected to a Stage output connection.

Background for “Pipelined analogue-to-digital (ADC), systems, methods and computer program products

“1. “1.

“The invention covers systems, methods and computer programs that relate to analog-to digital converters (ADCs), and more specifically to calibration systems, methods and computer program product relating to pipelined ADCs.

“2. “2.

The related art does not adequately address technical issues in calibrating pipelined analog to digital converters (ADCs). The related art focuses on the calibration of pipelined analog-to-digital converters (ADCs) using a capacitor array. This allows for calibration adjustments to alter the gain (R), of specific ADC stages, in order to meet a predetermined weighting relationship. Depending on the chosen weighting scheme, successive capacitors can be used to achieve this. In order to achieve high accuracy in ADC systems, it is necessary to use capacitors with prohibitive capacitance levels. A highly accurate ADC system, according to the related art, requires extremely small and very large capacitors. It is expensive and difficult to implement such a wide range of capacitance values with semiconductor materials.

“According one embodiment of the invention, a pipelined digital-to-analog converter (ADC), is calibrated to produce an n-bit digital output representing n-2 bits binary words, where?n? A large, positive integer that is selected without limitation to the order of ten (10). Each stage of a multistage analog to digital converter (ADC), according to the invention includes capacitor circuitry, including first and second predetermined capacitance capacitors (C1 & C2) and a variable capacitance calibr capacitor (Ccal), connected to an amplifier at a common point. A multistage ADC stage as per the present invention also includes a comparator and track and hold circuits. A multistage ADC system, according to one embodiment, includes at least four stages. Each stage contains a capacitor system that includes first and second predetermined capacitors, a calibration capacitor, an amplifier and a comparator. A tracker and source follower are also included. The present invention connects the capacitor system at a common node of the amplifier. The comparator is connected the the first predetermined capacitor. The tracker and source follower are connected the the output of amplifier. Finally, the source follower is connected the the comparator. A method according to the present invention involves a first predetermined capacitor coupled to a comparator. A second predetermined capacitor is connected to ground for each stage. Next, disconnect the first predetermined capacitor from each stage’s input connection and connect the second predetermined capacitor to each stage’s output. The output of each stage is then tracked and provided to the comparator for the next stage. This allows you to determine whether the voltage is higher or lower than the reference voltage.

Referring to FIG. “Referring now to FIG. 1, you will see a circuit diagram for an nth and a portion (n+1) of a pipelined digital-to-analog converter system (PADCS 99) according to the present invention. The (n+1th) stage of PADCS99 includes a track-and-hold circuit (THC), 11 according to the invention. Its output is the analog input (VIN) for the nthstage. The nth PADCS 99 stage includes a summation Node 102, an amp 103, a digital to-analog converter 104, a comparator 105 and a THC 101. The analog input voltage VIN is connected both to the comparator 105, and to summation nude 102. Summation node 102 connects to VIN and DAC 104 as its input, and to amplifier 103 as its output. The input of DAC 104 is connected to the output of comparator 105. The input of THC 101 is connected to amplifier 103. A pipeline stage can be described in general as FIG. 1. The input voltage is entered and then the comparator 105 receives it. The input voltage level is then compared to a chosen reference voltage. If the input voltage exceeds the reference voltage, the comparator105 generates a digital bits of one. If the input voltage falls below the reference voltage an output which is a digital bits of zero is generated. This digital bit is then sent to digital circuitry (not illustrated), which generates an ADC binary output, as well digital-to-analog convert 104. The output of this converter is the digital bit multiplied with a chosen reference voltage. This voltage is subtracted and then multiplied with a gain R. The output is connected to THC 101. According to one embodiment, R is greater than 1, but not more than 2. One embodiment of the present invention states that R has a value greater than 1.6. According to one embodiment, the transfer function for a pipelined ADC-system according to one embodiment is:

“Vout=R0*(R1*( . . . *(Rn?1*(Rn*(Vin ?b n)?. . . )?b 1)?b 0),?? (1)”

“where”

“Vout” is the output voltage of PADCS 99;

“Rn is gain at the nth stage.”

“Vin is an input voltage to PADCS99;”

“bn” is the nth of selected reference voltages that are provided to summation Node 102 from DAC 104;? ? V in = ? ????? ? ? + b 1 (R n )? R ( n- 1 ) ? ? ? ? R 2 +? ? b 0 (R n )? R ( n- 1 ) ? ? ? ? R 1 ) +V out ( R.n?) R ( n- 1 ) ? ? ? ? R 0?, ( 2 2)”

“where bn=DnVref(n); and”

“Dn” is the digital output from comparator 105.

Referring to FIG. “Referring now to FIG. 2, you will see a circuit diagram for a ten-stage ADC 199 according the present invention. It includes first and second comparators, 210, 211 that are used to generate twelve bits which map to a 10-bit binary words. ADC 199 contains the first and second comparators 210 and 211, as well as ten ADC stage (0-9), which respectively produce outputs D[0]?D[11] to signify a 10-bit binary phrase. The output of ADC stage n is the input to the (n?)th ADC Stage, while the output of stage zero is an input from each of comparators 220 and 211. Comparator 210 produces D[1] bit, and has a reference input that is twice the predetermined reference voltage Vref. Comparator 211 produces D[0] the zeroth output and has an input value of the predetermined voltage Vref. The gain value of an nth ADC stage has a value R, which is determined using calibration as follows. Gain calibration is an analog process and each ADC stage’s weight is digitally hard-coded. When a binary output word is being generated from an ADC stage, the weight is added to it.

“Thus, four ADC stages have binary weighting, with the output from the most-significant ADC Stage being one in magnitude. The final output word has a weight of 2**4, or 16.” Each ADC stage can be calibrated by setting its weight equal to the sum weights of the three preceding stages.

“Wn=Wn?1+Wn?2+Wn?3,?? (3)”

“where”

“Wn” is the weight of an ADC stage selected from nth;

“Wn?1” is the ADC stage’s weight immediately after the nth stage, which has a Wn;

“Wn.2” is the weight of ADC stage immediately following the (n.1)th stage, which has a Wn.1; and

“Wn.3” is the weight of ADC stage immediately following the (n.2)th stage, which has a Wn?2 weight.

The relationship between the gain Rn and a stage n is thus described as follows:

“Rn*Rn?1*Rn?2*Rn?3=Rn?1*Rn?2*Rn?3+Rn?2*Rn?3+Rn?3?? (4)”

“which generates a transfer function to the four-stage ADC of:

“Vout=Rn*Rn?1*Rn?2*Rn?3*Vin(n)?”

“Rn*Rn?1*Rn?2*Rn?3*Dn*Vref(n)?”

“Rn?1*Rn?2*Rn?3*Dn?1*Vref(n?1)?Rn?”

“2*Rn?3*Dn?2*Vref(n?2)?Rn?3*Dn?”

“3*Vref(n?2).?? (5)”

“Accordingly to the present invention, to satisfy equation 4, the calibration method sets D[n?(n?3)]=1000 equal with D[n?3)]=0111 by setting the output voltage of D[n?3]=1000.”

“D[n:(n?3)]=1000:Vout=Rn*Rn?1*Rn?2*Rn?3*Vin(n)?Rn*Rn?1*Rn?2*Rn?3*Vref(n).?? (6)”

“D[n:(n?3)]=0111:Vout=Rn*Rn?1*Rn?2*Rn?3*Vin(n)?Rn?1*Rn?2*Rn?3*Vref(n?1)?Rn?2*Rn?3*Vref(n?2)?Rn?3*Vref(n?2).?? (7)”

“It follows that:

“Rn*Rn?1*Rn?2*Rn?3*Vref(n)=Rn?1*Rn?2*Rn?3*Vref(n?1)+Rn?2*Rn?3*Vref(n?2)+Rn?3*Vref(n?2).?? (8)”

“Rn=[Vref(n?1)+Vref(n?2)/Rn?1+Vref(n?3)/(Rn?1*Rn?2)]/Vref(n).?? (9)”

The present invention allows for different reference voltages to be used in the different stages. According to the present invention, each stage’s weight is adjusted based on different reference potentials. This results in matching hard-coded digital settings. The gains from the more important stages are not affected by the presence of errors in the initial three lower stages that aren’t calibrated. Therefore, the digital logic of the present invention accepts a fixed setting for each state. This is even when there are some errors in the least-significant bits. This method of setting gains according to the present invention is used in one embodiment. The values of R9 andR0 can range from 1.839 to 1.860.

Referring to FIG. “Referring now to FIG. 3, you will see another circuit diagram for a single stage 299. This is one embodiment of the invention. A single stage 299 consists of the following: first through fourth switches 300, 301 and 332, and third through fourth capacitors 302-305 (three of them?302,304 and 305 being variable; and one capacitor?303 being fixed); an amplifier 307; a comparator 306; an AZ bypass toggle 308; feedback capacitor 309, a first control switch 311; a second switch 310; a track-and-hold cell (THC), 312; a source follower (313); and SF) circuit 314) Switch 301 connects the input voltage Vin to capacitors C1 (and Ccal) respectively 303, 304, and 335 during a first clock cycle. During the first clock phase, the AZ switches 308 & 310 are closed. This causes the amplifier 307’s unity gain to occur and one side of the capacitor 309 (C2) is connected to a reference earth (Vgnd). The input voltage Vin is connected with an input of comparator 306 and the value is compared against the comparator reference. The digital output Do will be a logically high value if the input voltage is higher than the reference voltage. The digital output will be a low value if the input voltage is greater than the reference voltage. The input of the amplifier 307 is connected to one side of C1 and Ccal capacitors, Cref, Coff and C2. C2 is connected in turn to the track and hold circuit (THC 312) which is in a hold condition during a first clock phase. The input of the THC 312 to the source follower circuit (363), and the input for the next ADC stage is the THC 312. If a cal_stg signal has a high value, the output of the SFC 313 can be connected to it. It will also tri-state if the signal has a low value. The input of the SFC 313 is connected to either Vgnd (or Vref) in a second clock phase. The output of the amplifier 307 then is in feedback. The THC 312 monitors the output of amplifier 307 in the second clock phase. The gain from the input is C1+Ccal/C2. This value is lower than 2, resulting in a redundancy. This redundancy allows comparator 306 references to be biased, so when comparator 306 outputs an error, it will most likely output a low than high value. This redundancy allows the remaining ADC states to recover from the low value error caused by the present invention.

Referring to FIG. 4A is a graph showing the transfer function for a comparator according the present invention without reference biasing. Particularly, FIG. FIG. 4A is a graph of Vin as a function Vout. It shows that the relationship between Vin and input voltage zero is linear, while segment 401 is linear between Vref and Vref. R Vref is also linear. This linear relationship holds between Vref input voltage and (R/ (R?1)Vref output voltage zero and R/ (R?1)Vref) Vmax. According to the invention, the input voltage of each stage is within the range of 0 and Vmax volts. The Vout value of any stage cannot be converted to a voltage lower than 0 or higher than Vmax.

Referring to FIG. 4B is a graph showing the transfer function for a comparator that includes reference biasing as per the present invention. FIG. FIG. 4B is a graph of Vout and Vin as a function of Vin. It shows the linear relationship along segment 410, the extension 411 thereof, between input voltage zero, [1+C]Vref and output voltage zero, and between d*Vref and d*Vref. The relationship between input voltage [1+C]Vref (R/?1)Vref) and output voltage [(2??R/?(R.1)]*Vref] is also linear. The transfer function can be adjusted to center Vmax between 0 and 0, so that there is a margin +/? [(1?0.5R]/(R?1)] Vref as illustrated in FIG. 4B. 4B. Accordingly, if the comparator/system has an offset, the system may recover so long as it is within the margins of error.

Referring to FIG. “Referring now to FIG. 5A, you will see a conceptual circuit diagram for a PADCS 490 with pipelined ADC stage according to the present invention. PADCS 490, in particular, includes the nth, (n?)th, and zeroth ADC stage respectively 491, 492, and 493. Nth ADC stage 491 contains first and second summation nosdes, respectively 502 and 501. A comparator 503 is also included and an amplifier 504. (N?1)th ADC Stage 492 includes first- and second summation nosdes, respectively 511 and 522, a comparator 513 and an amplifier 514. Zeroth ADC stage 493 contains first and second summation nosdes, respectively 521, 522, a comparator 533, and an amplifier 524. The nth ADC Stage 491 is connected to an input voltage Vin, and outputs a voltage at amplifier 504 to a 1summing node 511. The input voltage to the (n?1)th ADC Stage 492 is from amplifier 504. The output voltage of the immediately preceding amplifier (504 is not shown) provides an input voltage to the zeroth ADC stage 493. The present invention provides an offset for each summation node, e.g. On, O(n?)1. . . as applicable. Each stage 491-493 includes a comparator offset. This is i.e. CN, C (N?1), or C0 at the input of respective comparator 513, 513, and 523.

Referring to FIG. “Referring now to FIG. 5B, you will see a conceptual circuit diagram for a PADCS490 of pipelined ADC stage according to the present invention with offsets mixed at the ADC inputs. Particularly, PADCS 500 contains n-th (n?1)th and zeroth ADC stage respectively 494, 595, and 496. Nth ADC stage 494 contains first and second summation nosdes, respectively 601 and 502, a comparator 503 as well as an amplifier 504. (N?1)th ADC Stage 495 includes the first and second summation nosdes, respectively 611 and 502. A comparator 513 is used and an amplifier 514 is used. Zeroth ADC stage 496 comprises first and second summation nosdes, respectively 621 and 522, and a comparator 523 as well as an amplifier 524. The nth ADC stage 494 receives an input and offset voltage VIN+(ON+O(N?1)/RN+O(N?2)/(RN*R(N?1))+ . . . ) at the inputs of the first and second summation nosdes 611, 502. A comparator offset of CN 502 is also provided to the second summation number 502. (On+O(N?1)/RN+ . . . ). The output voltage of amplifier 504 is received by the (n?1)th ADC Stage 495. Second summation node 512, which receives a composite input with an offset of C?1?, receives an input from the second summation stage 512. [O(N?1)+O(N?2)/R(N?1)+ . . . ]. The input voltage to the zeroth ADC stage 493 is received from amplifier 614’s output. Second summation node 522, on the other hand, receives a composite input with an offset of C0.O0. FIG. FIG. 5B shows that system offsets are combined at the ADC input to aid in analysis. According to the invention, the offset for a stage is subtracted from its comparator offset. The system will function as intended as long as the total offset into the comparator is within the error margin. The comparators can use the additional allowance for offsets provided by redundancy by cancelling most of the system offset. You can correct the system offset using the below-described offset cancellation procedure.

Referring to FIG. “Referring now to FIG. 6, is a diagram showing the offset capacitors for a single stage 599 in a pipelined ADC systems, according the present invention. ADC stage 599 also includes switches 601-605 that are open and closed depending on the product of phase (or O0*?) ADC stage 599 also includes capacitors 511-514 and amplifier 307, bypass circuit 308 and feedback capacitor 309(C2), as well as first and second switches 621-621. The input of amplifier 307 is connected to capacitors 601-617. The corresponding capacitors 511-514 are connected to the switches 601-604. The capacitors 616 and 617 are connected together, and the capacitances of 617 and 615 can be adjusted according to the invention. The calibration comparator reference for the MSB stage is set to Vgnd. Vgnd is the input to ADC. One conversion cycle occurs. The output of the MSB stage can be compared with the reference calibration comparator. If the output exceeds the reference, there will be a positive offset. A negative offset must then be added to compensate for the charge that was added during the second phase. The negative capacitor switch is set so the capacitor is in circuit. The largest positive capacitor switch should be set so that the capacitor is present in the circuit. This will add charge to the clock’s first phase. One conversion cycle occurs. The output of the MSB stage can then be compared with the reference calibration comparator. If the output exceeds the reference, the switch will turn off. If the output is greater than the reference, then the switch should be turned off. For the remaining positive capacitors, repeat the set-and-test procedure. After the system offset has been cancelled, each ADC stage’s gain is calibrated.

Referring to FIG. “Referring now to FIG. 7, you will see a circuit diagram showing the last four stages of a pipelined ADC systems 690 according the present invention. ADC system 690 consists of the third, second, first, and zeroth ADC stage, respectively 691-694. The third ADC stage 691 comprises the first and second capacitors 701 & 703, an amplifier 702, and switch 704, as well as a track-and-hold circuit (THC 705) 705. The input of the third ADC stage 691 connects to ground (i.e. Vgnd) at capacitor 701. THC 705 and amplifier 702 are connected in series. The amplifier 702, capacitor 703 and the switch 704 are connected in parallel. ADC system 690 also includes the first, second, or third switches 750-752 connecting said third and fourth, said second and initial, and said first and zeroth ADC stage. The second ADC stage 692 comprises the first and second capacitors 711, 713, and an amplifier 712 as well as a switch 714, THC 715, and a THC 715. In series, capacitor 711, amplifier 712 & THC 715 are connected. The parallel connections of amplifier 712, capacitor 713 and switch 714 are made to each other. The first ADC stage 693 comprises the first and second capacitors 721, 723, and an amplifier 722, as well as a switch 724 and a THC 725. THC 725, amplifier 722, capacitor 721, and amplifier 722 are all connected in series. The amplifier 722, capacitor 723 and the switch 724 are connected in parallel. Zeroth ADC stage 694 comprises first and second capacitors 731, 733, an amplifier 732, switch 734 and THC 735. In series, capacitor 731, amplifier 732 and THC 735 are connected. The parallel connections of amplifier 732, capacitor 733 and switch 734 are made to one another. The switch 750 is connected to THC 705; the switch 751 connects between THC 705 and capacitor 721; while switch 752 connects between THC 725, capacitor 721 and switch 752.

Referring to FIG. “Referring now to FIG. 8, you will see a circuit diagram showing the last four steps of the pipelined ADC system 690 as per the present invention. ADC system 690 consists of third, second and first ADC stages, respectively 691-694. The third ADC stage 691 comprises the first and second capacitors 701 & 703, an amplifier 702, and a switch 704, as well as a THC 705. A switch 800 connects to ADC system 690’s input and capacitor 701. Switch 800 can be used to toggle between Vref or Vgnd during the respective clock phases. ADC system 690 also includes the first, second and third switches 750.751. and 752. These are used to connect said third, second and first ADC stages. The second ADC stage 692 comprises first and second capacitors 711, 713, an amplifier 712, a switch 714 and a THC-715. THC 715, amplifier 712 and capacitor 711 are connected in series. The parallel connections of amplifier 712, capacitor 713 and switch 714 are made to each other. The first ADC stage 693 comprises the first and second capacitors 721, 723, and an amplifier 722, as well as a switch 724 and a THC 725. THC 723, amplifier 722, capacitor 721, and amplifier 722 are all connected in series. The amplifier 722, capacitor 723, and switch 724 are connected in parallel. Zeroth ADC stage 694 comprises first and second capacitors 731, 733, an amplifier 732, switch 734 and THC 735. In series, capacitor 731, amplifier 732 and THC 735 are connected. The parallel connections between amplifier 732, capacitor 733, and switch 734 are amplifier 732, 733, and 733 respectively. The switch 750 is connected between THC 705 (capacitor 711), and the switch 734. Switch 751 connects between THC 705 and capacitor 711. Switch 752 connects between THC 725 & capacitor 731.

Adjustments are made to the reference and sampling capacitors, as these implements must be identical for most of their range or the corrections required can grow beyond bounds. The three most significant bits of the calibration capacitors can be connected to the input only. To achieve greater precision, the reference voltage can be used to scale down the capacitors.

Referring to FIG. “Referring again to FIG. 7, is shown a procedure that the present invention uses to calibrate each stage’s gain. The ADC system’s three lowest stages have fixed gains of 7/4, 2 and 2 respectively for stages one, two, and zero (third-most significant, second-most significant, and least-significant bits). Stage three is the first stage that can be calibrated in accordance with the present invention. The third stage samples Vgnd for four cycles including the first clock phase. Stages two, one, and zero then sample their voltage inputs. The second clock phase sees stage three’s sampling capacitors remain at Vgnd. Stages two through zero switch their sampling capacitors to Vgnd during the second clock phase. This dumps charge onto the feedback capacitor C2. After these four clock cycles, stage zero will output the combined offset of all four stages OTOT. This value is saved in the reference memory of the calibration comparator. The second stage sees the first calibration capacitor being switched parallel to C1 during phase three. The third cycle samples Vref in phase one, and Vgnd in phase two. The stages two through zero collect their inputs during phase one, and Vref during Phase 2. FIG. 8. The output of stage zero is then R3*R2*R1*R0*Vref(3)?R2*R1*R0*Vref(2)?R1*R0*Vref(1)?R0*Vref(0)+OTOT. From this, it can be seen that if R3*R2*R1*R0*Vref(3)=R2*R1*R0*Vref(2)+R1*R0*Vref(1)?R0*Vref(0), then the output of stage zero will be OTOT. This is fourthly compared with the reference calibration comparator, which is OTOT. If stage zero’s output is lower than OTOT, R3 will be too small. The capacitor will remain parallel to C1. R3 is too big and the capacitor is removed from the data path if the output exceeds OTOT. The fifth and final operation is repeated for all remaining capacitors in both the reference and calibration capacitor arrays according to the invention. Sixth, the operation proceeds to the next preceding stage (i.e. four after three is completed) and then the operations one through five are again repeated.

Summary for “Pipelined analogue-to-digital (ADC), systems, methods and computer program products

“1. “1.

“The invention covers systems, methods and computer programs that relate to analog-to digital converters (ADCs), and more specifically to calibration systems, methods and computer program product relating to pipelined ADCs.

“2. “2.

The related art does not adequately address technical issues in calibrating pipelined analog to digital converters (ADCs). The related art focuses on the calibration of pipelined analog-to-digital converters (ADCs) using a capacitor array. This allows for calibration adjustments to alter the gain (R), of specific ADC stages, in order to meet a predetermined weighting relationship. Depending on the chosen weighting scheme, successive capacitors can be used to achieve this. In order to achieve high accuracy in ADC systems, it is necessary to use capacitors with prohibitive capacitance levels. A highly accurate ADC system, according to the related art, requires extremely small and very large capacitors. It is expensive and difficult to implement such a wide range of capacitance values with semiconductor materials.

“According one embodiment of the invention, a pipelined digital-to-analog converter (ADC), is calibrated to produce an n-bit digital output representing n-2 bits binary words, where?n? A large, positive integer that is selected without limitation to the order of ten (10). Each stage of a multistage analog to digital converter (ADC), according to the invention includes capacitor circuitry, including first and second predetermined capacitance capacitors (C1 & C2) and a variable capacitance calibr capacitor (Ccal), connected to an amplifier at a common point. A multistage ADC stage as per the present invention also includes a comparator and track and hold circuits. A multistage ADC system, according to one embodiment, includes at least four stages. Each stage contains a capacitor system that includes first and second predetermined capacitors, a calibration capacitor, an amplifier and a comparator. A tracker and source follower are also included. The present invention connects the capacitor system at a common node of the amplifier. The comparator is connected the the first predetermined capacitor. The tracker and source follower are connected the the output of amplifier. Finally, the source follower is connected the the comparator. A method according to the present invention involves a first predetermined capacitor coupled to a comparator. A second predetermined capacitor is connected to ground for each stage. Next, disconnect the first predetermined capacitor from each stage’s input connection and connect the second predetermined capacitor to each stage’s output. The output of each stage is then tracked and provided to the comparator for the next stage. This allows you to determine whether the voltage is higher or lower than the reference voltage.

Referring to FIG. “Referring now to FIG. 1, you will see a circuit diagram for an nth and a portion (n+1) of a pipelined digital-to-analog converter system (PADCS 99) according to the present invention. The (n+1th) stage of PADCS99 includes a track-and-hold circuit (THC), 11 according to the invention. Its output is the analog input (VIN) for the nthstage. The nth PADCS 99 stage includes a summation Node 102, an amp 103, a digital to-analog converter 104, a comparator 105 and a THC 101. The analog input voltage VIN is connected both to the comparator 105, and to summation nude 102. Summation node 102 connects to VIN and DAC 104 as its input, and to amplifier 103 as its output. The input of DAC 104 is connected to the output of comparator 105. The input of THC 101 is connected to amplifier 103. A pipeline stage can be described in general as FIG. 1. The input voltage is entered and then the comparator 105 receives it. The input voltage level is then compared to a chosen reference voltage. If the input voltage exceeds the reference voltage, the comparator105 generates a digital bits of one. If the input voltage falls below the reference voltage an output which is a digital bits of zero is generated. This digital bit is then sent to digital circuitry (not illustrated), which generates an ADC binary output, as well digital-to-analog convert 104. The output of this converter is the digital bit multiplied with a chosen reference voltage. This voltage is subtracted and then multiplied with a gain R. The output is connected to THC 101. According to one embodiment, R is greater than 1, but not more than 2. One embodiment of the present invention states that R has a value greater than 1.6. According to one embodiment, the transfer function for a pipelined ADC-system according to one embodiment is:

“Vout=R0*(R1*( . . . *(Rn?1*(Rn*(Vin ?b n)?. . . )?b 1)?b 0),?? (1)”

“where”

“Vout” is the output voltage of PADCS 99;

“Rn is gain at the nth stage.”

“Vin is an input voltage to PADCS99;”

“bn” is the nth of selected reference voltages that are provided to summation Node 102 from DAC 104;? ? V in = ? ????? ? ? + b 1 (R n )? R ( n- 1 ) ? ? ? ? R 2 +? ? b 0 (R n )? R ( n- 1 ) ? ? ? ? R 1 ) +V out ( R.n?) R ( n- 1 ) ? ? ? ? R 0?, ( 2 2)”

“where bn=DnVref(n); and”

“Dn” is the digital output from comparator 105.

Referring to FIG. “Referring now to FIG. 2, you will see a circuit diagram for a ten-stage ADC 199 according the present invention. It includes first and second comparators, 210, 211 that are used to generate twelve bits which map to a 10-bit binary words. ADC 199 contains the first and second comparators 210 and 211, as well as ten ADC stage (0-9), which respectively produce outputs D[0]?D[11] to signify a 10-bit binary phrase. The output of ADC stage n is the input to the (n?)th ADC Stage, while the output of stage zero is an input from each of comparators 220 and 211. Comparator 210 produces D[1] bit, and has a reference input that is twice the predetermined reference voltage Vref. Comparator 211 produces D[0] the zeroth output and has an input value of the predetermined voltage Vref. The gain value of an nth ADC stage has a value R, which is determined using calibration as follows. Gain calibration is an analog process and each ADC stage’s weight is digitally hard-coded. When a binary output word is being generated from an ADC stage, the weight is added to it.

“Thus, four ADC stages have binary weighting, with the output from the most-significant ADC Stage being one in magnitude. The final output word has a weight of 2**4, or 16.” Each ADC stage can be calibrated by setting its weight equal to the sum weights of the three preceding stages.

“Wn=Wn?1+Wn?2+Wn?3,?? (3)”

“where”

“Wn” is the weight of an ADC stage selected from nth;

“Wn?1” is the ADC stage’s weight immediately after the nth stage, which has a Wn;

“Wn.2” is the weight of ADC stage immediately following the (n.1)th stage, which has a Wn.1; and

“Wn.3” is the weight of ADC stage immediately following the (n.2)th stage, which has a Wn?2 weight.

The relationship between the gain Rn and a stage n is thus described as follows:

“Rn*Rn?1*Rn?2*Rn?3=Rn?1*Rn?2*Rn?3+Rn?2*Rn?3+Rn?3?? (4)”

“which generates a transfer function to the four-stage ADC of:

“Vout=Rn*Rn?1*Rn?2*Rn?3*Vin(n)?”

“Rn*Rn?1*Rn?2*Rn?3*Dn*Vref(n)?”

“Rn?1*Rn?2*Rn?3*Dn?1*Vref(n?1)?Rn?”

“2*Rn?3*Dn?2*Vref(n?2)?Rn?3*Dn?”

“3*Vref(n?2).?? (5)”

“Accordingly to the present invention, to satisfy equation 4, the calibration method sets D[n?(n?3)]=1000 equal with D[n?3)]=0111 by setting the output voltage of D[n?3]=1000.”

“D[n:(n?3)]=1000:Vout=Rn*Rn?1*Rn?2*Rn?3*Vin(n)?Rn*Rn?1*Rn?2*Rn?3*Vref(n).?? (6)”

“D[n:(n?3)]=0111:Vout=Rn*Rn?1*Rn?2*Rn?3*Vin(n)?Rn?1*Rn?2*Rn?3*Vref(n?1)?Rn?2*Rn?3*Vref(n?2)?Rn?3*Vref(n?2).?? (7)”

“It follows that:

“Rn*Rn?1*Rn?2*Rn?3*Vref(n)=Rn?1*Rn?2*Rn?3*Vref(n?1)+Rn?2*Rn?3*Vref(n?2)+Rn?3*Vref(n?2).?? (8)”

“Rn=[Vref(n?1)+Vref(n?2)/Rn?1+Vref(n?3)/(Rn?1*Rn?2)]/Vref(n).?? (9)”

The present invention allows for different reference voltages to be used in the different stages. According to the present invention, each stage’s weight is adjusted based on different reference potentials. This results in matching hard-coded digital settings. The gains from the more important stages are not affected by the presence of errors in the initial three lower stages that aren’t calibrated. Therefore, the digital logic of the present invention accepts a fixed setting for each state. This is even when there are some errors in the least-significant bits. This method of setting gains according to the present invention is used in one embodiment. The values of R9 andR0 can range from 1.839 to 1.860.

Referring to FIG. “Referring now to FIG. 3, you will see another circuit diagram for a single stage 299. This is one embodiment of the invention. A single stage 299 consists of the following: first through fourth switches 300, 301 and 332, and third through fourth capacitors 302-305 (three of them?302,304 and 305 being variable; and one capacitor?303 being fixed); an amplifier 307; a comparator 306; an AZ bypass toggle 308; feedback capacitor 309, a first control switch 311; a second switch 310; a track-and-hold cell (THC), 312; a source follower (313); and SF) circuit 314) Switch 301 connects the input voltage Vin to capacitors C1 (and Ccal) respectively 303, 304, and 335 during a first clock cycle. During the first clock phase, the AZ switches 308 & 310 are closed. This causes the amplifier 307’s unity gain to occur and one side of the capacitor 309 (C2) is connected to a reference earth (Vgnd). The input voltage Vin is connected with an input of comparator 306 and the value is compared against the comparator reference. The digital output Do will be a logically high value if the input voltage is higher than the reference voltage. The digital output will be a low value if the input voltage is greater than the reference voltage. The input of the amplifier 307 is connected to one side of C1 and Ccal capacitors, Cref, Coff and C2. C2 is connected in turn to the track and hold circuit (THC 312) which is in a hold condition during a first clock phase. The input of the THC 312 to the source follower circuit (363), and the input for the next ADC stage is the THC 312. If a cal_stg signal has a high value, the output of the SFC 313 can be connected to it. It will also tri-state if the signal has a low value. The input of the SFC 313 is connected to either Vgnd (or Vref) in a second clock phase. The output of the amplifier 307 then is in feedback. The THC 312 monitors the output of amplifier 307 in the second clock phase. The gain from the input is C1+Ccal/C2. This value is lower than 2, resulting in a redundancy. This redundancy allows comparator 306 references to be biased, so when comparator 306 outputs an error, it will most likely output a low than high value. This redundancy allows the remaining ADC states to recover from the low value error caused by the present invention.

Referring to FIG. 4A is a graph showing the transfer function for a comparator according the present invention without reference biasing. Particularly, FIG. FIG. 4A is a graph of Vin as a function Vout. It shows that the relationship between Vin and input voltage zero is linear, while segment 401 is linear between Vref and Vref. R Vref is also linear. This linear relationship holds between Vref input voltage and (R/ (R?1)Vref output voltage zero and R/ (R?1)Vref) Vmax. According to the invention, the input voltage of each stage is within the range of 0 and Vmax volts. The Vout value of any stage cannot be converted to a voltage lower than 0 or higher than Vmax.

Referring to FIG. 4B is a graph showing the transfer function for a comparator that includes reference biasing as per the present invention. FIG. FIG. 4B is a graph of Vout and Vin as a function of Vin. It shows the linear relationship along segment 410, the extension 411 thereof, between input voltage zero, [1+C]Vref and output voltage zero, and between d*Vref and d*Vref. The relationship between input voltage [1+C]Vref (R/?1)Vref) and output voltage [(2??R/?(R.1)]*Vref] is also linear. The transfer function can be adjusted to center Vmax between 0 and 0, so that there is a margin +/? [(1?0.5R]/(R?1)] Vref as illustrated in FIG. 4B. 4B. Accordingly, if the comparator/system has an offset, the system may recover so long as it is within the margins of error.

Referring to FIG. “Referring now to FIG. 5A, you will see a conceptual circuit diagram for a PADCS 490 with pipelined ADC stage according to the present invention. PADCS 490, in particular, includes the nth, (n?)th, and zeroth ADC stage respectively 491, 492, and 493. Nth ADC stage 491 contains first and second summation nosdes, respectively 502 and 501. A comparator 503 is also included and an amplifier 504. (N?1)th ADC Stage 492 includes first- and second summation nosdes, respectively 511 and 522, a comparator 513 and an amplifier 514. Zeroth ADC stage 493 contains first and second summation nosdes, respectively 521, 522, a comparator 533, and an amplifier 524. The nth ADC Stage 491 is connected to an input voltage Vin, and outputs a voltage at amplifier 504 to a 1summing node 511. The input voltage to the (n?1)th ADC Stage 492 is from amplifier 504. The output voltage of the immediately preceding amplifier (504 is not shown) provides an input voltage to the zeroth ADC stage 493. The present invention provides an offset for each summation node, e.g. On, O(n?)1. . . as applicable. Each stage 491-493 includes a comparator offset. This is i.e. CN, C (N?1), or C0 at the input of respective comparator 513, 513, and 523.

Referring to FIG. “Referring now to FIG. 5B, you will see a conceptual circuit diagram for a PADCS490 of pipelined ADC stage according to the present invention with offsets mixed at the ADC inputs. Particularly, PADCS 500 contains n-th (n?1)th and zeroth ADC stage respectively 494, 595, and 496. Nth ADC stage 494 contains first and second summation nosdes, respectively 601 and 502, a comparator 503 as well as an amplifier 504. (N?1)th ADC Stage 495 includes the first and second summation nosdes, respectively 611 and 502. A comparator 513 is used and an amplifier 514 is used. Zeroth ADC stage 496 comprises first and second summation nosdes, respectively 621 and 522, and a comparator 523 as well as an amplifier 524. The nth ADC stage 494 receives an input and offset voltage VIN+(ON+O(N?1)/RN+O(N?2)/(RN*R(N?1))+ . . . ) at the inputs of the first and second summation nosdes 611, 502. A comparator offset of CN 502 is also provided to the second summation number 502. (On+O(N?1)/RN+ . . . ). The output voltage of amplifier 504 is received by the (n?1)th ADC Stage 495. Second summation node 512, which receives a composite input with an offset of C?1?, receives an input from the second summation stage 512. [O(N?1)+O(N?2)/R(N?1)+ . . . ]. The input voltage to the zeroth ADC stage 493 is received from amplifier 614’s output. Second summation node 522, on the other hand, receives a composite input with an offset of C0.O0. FIG. FIG. 5B shows that system offsets are combined at the ADC input to aid in analysis. According to the invention, the offset for a stage is subtracted from its comparator offset. The system will function as intended as long as the total offset into the comparator is within the error margin. The comparators can use the additional allowance for offsets provided by redundancy by cancelling most of the system offset. You can correct the system offset using the below-described offset cancellation procedure.

Referring to FIG. “Referring now to FIG. 6, is a diagram showing the offset capacitors for a single stage 599 in a pipelined ADC systems, according the present invention. ADC stage 599 also includes switches 601-605 that are open and closed depending on the product of phase (or O0*?) ADC stage 599 also includes capacitors 511-514 and amplifier 307, bypass circuit 308 and feedback capacitor 309(C2), as well as first and second switches 621-621. The input of amplifier 307 is connected to capacitors 601-617. The corresponding capacitors 511-514 are connected to the switches 601-604. The capacitors 616 and 617 are connected together, and the capacitances of 617 and 615 can be adjusted according to the invention. The calibration comparator reference for the MSB stage is set to Vgnd. Vgnd is the input to ADC. One conversion cycle occurs. The output of the MSB stage can be compared with the reference calibration comparator. If the output exceeds the reference, there will be a positive offset. A negative offset must then be added to compensate for the charge that was added during the second phase. The negative capacitor switch is set so the capacitor is in circuit. The largest positive capacitor switch should be set so that the capacitor is present in the circuit. This will add charge to the clock’s first phase. One conversion cycle occurs. The output of the MSB stage can then be compared with the reference calibration comparator. If the output exceeds the reference, the switch will turn off. If the output is greater than the reference, then the switch should be turned off. For the remaining positive capacitors, repeat the set-and-test procedure. After the system offset has been cancelled, each ADC stage’s gain is calibrated.

Referring to FIG. “Referring now to FIG. 7, you will see a circuit diagram showing the last four stages of a pipelined ADC systems 690 according the present invention. ADC system 690 consists of the third, second, first, and zeroth ADC stage, respectively 691-694. The third ADC stage 691 comprises the first and second capacitors 701 & 703, an amplifier 702, and switch 704, as well as a track-and-hold circuit (THC 705) 705. The input of the third ADC stage 691 connects to ground (i.e. Vgnd) at capacitor 701. THC 705 and amplifier 702 are connected in series. The amplifier 702, capacitor 703 and the switch 704 are connected in parallel. ADC system 690 also includes the first, second, or third switches 750-752 connecting said third and fourth, said second and initial, and said first and zeroth ADC stage. The second ADC stage 692 comprises the first and second capacitors 711, 713, and an amplifier 712 as well as a switch 714, THC 715, and a THC 715. In series, capacitor 711, amplifier 712 & THC 715 are connected. The parallel connections of amplifier 712, capacitor 713 and switch 714 are made to each other. The first ADC stage 693 comprises the first and second capacitors 721, 723, and an amplifier 722, as well as a switch 724 and a THC 725. THC 725, amplifier 722, capacitor 721, and amplifier 722 are all connected in series. The amplifier 722, capacitor 723 and the switch 724 are connected in parallel. Zeroth ADC stage 694 comprises first and second capacitors 731, 733, an amplifier 732, switch 734 and THC 735. In series, capacitor 731, amplifier 732 and THC 735 are connected. The parallel connections of amplifier 732, capacitor 733 and switch 734 are made to one another. The switch 750 is connected to THC 705; the switch 751 connects between THC 705 and capacitor 721; while switch 752 connects between THC 725, capacitor 721 and switch 752.

Referring to FIG. “Referring now to FIG. 8, you will see a circuit diagram showing the last four steps of the pipelined ADC system 690 as per the present invention. ADC system 690 consists of third, second and first ADC stages, respectively 691-694. The third ADC stage 691 comprises the first and second capacitors 701 & 703, an amplifier 702, and a switch 704, as well as a THC 705. A switch 800 connects to ADC system 690’s input and capacitor 701. Switch 800 can be used to toggle between Vref or Vgnd during the respective clock phases. ADC system 690 also includes the first, second and third switches 750.751. and 752. These are used to connect said third, second and first ADC stages. The second ADC stage 692 comprises first and second capacitors 711, 713, an amplifier 712, a switch 714 and a THC-715. THC 715, amplifier 712 and capacitor 711 are connected in series. The parallel connections of amplifier 712, capacitor 713 and switch 714 are made to each other. The first ADC stage 693 comprises the first and second capacitors 721, 723, and an amplifier 722, as well as a switch 724 and a THC 725. THC 723, amplifier 722, capacitor 721, and amplifier 722 are all connected in series. The amplifier 722, capacitor 723, and switch 724 are connected in parallel. Zeroth ADC stage 694 comprises first and second capacitors 731, 733, an amplifier 732, switch 734 and THC 735. In series, capacitor 731, amplifier 732 and THC 735 are connected. The parallel connections between amplifier 732, capacitor 733, and switch 734 are amplifier 732, 733, and 733 respectively. The switch 750 is connected between THC 705 (capacitor 711), and the switch 734. Switch 751 connects between THC 705 and capacitor 711. Switch 752 connects between THC 725 & capacitor 731.

Adjustments are made to the reference and sampling capacitors, as these implements must be identical for most of their range or the corrections required can grow beyond bounds. The three most significant bits of the calibration capacitors can be connected to the input only. To achieve greater precision, the reference voltage can be used to scale down the capacitors.

Referring to FIG. “Referring again to FIG. 7, is shown a procedure that the present invention uses to calibrate each stage’s gain. The ADC system’s three lowest stages have fixed gains of 7/4, 2 and 2 respectively for stages one, two, and zero (third-most significant, second-most significant, and least-significant bits). Stage three is the first stage that can be calibrated in accordance with the present invention. The third stage samples Vgnd for four cycles including the first clock phase. Stages two, one, and zero then sample their voltage inputs. The second clock phase sees stage three’s sampling capacitors remain at Vgnd. Stages two through zero switch their sampling capacitors to Vgnd during the second clock phase. This dumps charge onto the feedback capacitor C2. After these four clock cycles, stage zero will output the combined offset of all four stages OTOT. This value is saved in the reference memory of the calibration comparator. The second stage sees the first calibration capacitor being switched parallel to C1 during phase three. The third cycle samples Vref in phase one, and Vgnd in phase two. The stages two through zero collect their inputs during phase one, and Vref during Phase 2. FIG. 8. The output of stage zero is then R3*R2*R1*R0*Vref(3)?R2*R1*R0*Vref(2)?R1*R0*Vref(1)?R0*Vref(0)+OTOT. From this, it can be seen that if R3*R2*R1*R0*Vref(3)=R2*R1*R0*Vref(2)+R1*R0*Vref(1)?R0*Vref(0), then the output of stage zero will be OTOT. This is fourthly compared with the reference calibration comparator, which is OTOT. If stage zero’s output is lower than OTOT, R3 will be too small. The capacitor will remain parallel to C1. R3 is too big and the capacitor is removed from the data path if the output exceeds OTOT. The fifth and final operation is repeated for all remaining capacitors in both the reference and calibration capacitor arrays according to the invention. Sixth, the operation proceeds to the next preceding stage (i.e. four after three is completed) and then the operations one through five are again repeated.

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